This disclosure relates to driving controllers and internal voltage generation circuit.
Semiconductor memories generally use internal operation voltages made from power source voltages and ground voltages which are supplied from external systems. Such internal voltages are oftentimes core voltages supplied into core regions, high voltages for driving word lines or for overdriving, back bias voltages supplied into bulks of NMOS transistors of the core regions, and so on.
An internal voltage generation circuit usually comprises a standby driver for providing internal voltages in a standby mode, and an active driver for providing internal voltages in an active mode. The reason of additionally furnishing the standby driver to activate the internal voltages in the standby mode is for reducing power consumption by exclusively activating the standby driver, which can be driven in low power, in the standby mode during which there an operation of reading or writing is being substantially inactive.
FIGS. 1 and 2 show an initial operation of an internal voltage in a semiconductor memory apparatus.
As shown by voltage waveforms of FIG. 1, if the semiconductor memory apparatus begins to operate, an external power source voltage VDD initially starts low and rises to a working stable level. In a semiconductor memory apparatus using the external power source voltage VDD of 1.8V, a normal operation can be enabled when the external power source voltage VDD reaches 1.0 ˜1.2V. Thus, a power-up signal PWRUP is generated to rises up to the same level with the external power source voltage VDD in a power-up period between time A0 to time A1. After the power-up period, the power-up signal PWRUP drops down to a low level. Accordingly, the semiconductor memory apparatus is set to start a normal operation after the power-up signal PWRUP transitions back to a low level. As also for an internal voltage VINT, the internal voltage VINT is driven to rise up along the external power source voltage VDD during the power-up period between times A0 to A1. During a period between times A1 to A2, after the power-up period, the internal voltage VINT is driven to rapidly rise up to a predetermined level by activation of an internal voltage generation circuit. That is, as shown by a waveform X in the graph of FIG. 2, when the external power source voltage VDD reaches about 1.0˜1.2V in the condition with sufficient drivability for the internal voltage VINT, then the internal voltage VINT rapidly rises up to the predetermined level by operation of the internal voltage generation circuit.
However, since the semiconductor memory apparatus is still operating in the standby mode during the period from A1 to A2 even after the power-up period and a standby driver is being active alone in the internal voltage generation circuit, then insufficient drivability to the internal voltage VINT could happen to the semiconductor memory apparatus. In this case, as shown by waveforms Y and Z of FIG. 2, the internal voltage VINT is permitted to rise up to the predetermined level only when the external power source voltage VDD elevates to a level higher than 1.3V. If the drivability for the internal voltage VINT is insufficient, then a functional fail (i.e., malfunction) can occur since the internal voltage VINT is being held in a low level, which is incapable of immediately rising up to the predetermined level, even after the power-up period between A0˜A1. Such a failure would be more conspicuous in a semiconductor memory apparatus where the power-up period is set at a relatively short time period.